module breath_led
#
(
    parameter START_FREQ_STEP = 10'd1
)
(
    input wire clk,
    input wire rstn,
    input wire sw_ctrl,
    input wire set_en,
    input wire [9 : 0] set_freq_step,
    output wire led
);
parameter CNT_2US_MAX = 7'd100;
parameter CNT_2MS_MAX = 10'd1000;
parameter CNT_2S_MAX = 10'd1000;
reg [6 : 0] cnt_2us;
reg [9 : 0] cnt_2ms;
reg [9 : 0] cnt_2s;
reg inc_dec_flag;
reg [9 : 0] freq_step;
reg led_t;
assign led = led_t & sw_ctrl;
always @(posedge clk or negedge rstn) begin
    if (!rstn)
        freq_step <= START_FREQ_STEP;
    else if (set_freq_step == 0)
        freq_step <= 10'd1;
    else if (set_freq_step > 10)
        freq_step <= 10'd10;
    else
        freq_step <= set_freq_step;
end
always @(posedge clk or negedge rstn) begin
    if (!rstn)
        cnt_2us <= 7'b0;
    else if (cnt_2us == (CNT_2US_MAX - 1))
        cnt_2us <= 7'b0;
    else
        cnt_2us <= cnt_2us + 1'b1;
end
always @(posedge clk or negedge rstn) begin
    if (!rstn)
        cnt_2ms <= 10'b0;
    else if (cnt_2ms == (CNT_2MS_MAX - 1) && cnt_2us == (CNT_2US_MAX - 1))
        cnt_2ms <= 10'b0;
    else if (cnt_2us == (CNT_2US_MAX - 1))
        cnt_2ms <= cnt_2ms + 1'b1;
end
always @(posedge clk or negedge rstn) begin
    if (!rstn)
        cnt_2s <= 10'b0;
    else if (cnt_2s == (CNT_2S_MAX - 1) && cnt_2ms == (CNT_2MS_MAX - 1) && cnt_2us == (CNT_2US_MAX - 1))
        cnt_2s <= 10'b0;
    else if (cnt_2ms == (CNT_2MS_MAX - 1) && cnt_2us == (CNT_2US_MAX - 1))
        cnt_2s <= cnt_2s + 1'b1;
end
always @(posedge clk or negedge rstn) begin
    if (!rstn)
        inc_dec_flag <= 1'b0;
    else if (cnt_2s == (CNT_2S_MAX - 1) && cnt_2ms == (CNT_2MS_MAX - 1) && cnt_2us == (CNT_2US_MAX - 1))
        inc_dec_flag <= ~inc_dec_flag;
    else
        inc_dec_flag <= inc_dec_flag;
end
always @(posedge clk or negedge rstn) begin
    if (!rstn)
        led_t <= 1'b0;
    else if (inc_dec_flag && cnt_2ms >= cnt_2s)
        led_t <= 1'b1;
    else if (!inc_dec_flag && cnt_2ms < cnt_2s)
        led_t <= 1'b1;
    else
        led_t <= 1'b0;
end
endmodule
